A comparator compares two inputs and takes a binary decision. Latched comparators are driven by a clock signal, allowing for resetting the circuitry ahead of each comparison.
Latched comparators employing a dynamic pre-amplifier stage are known for their low power consumption, since their dominant sub-threshold operation and no DC bias current makes the power consumption only proportional to the operating frequency. Further, the pre-amplifier stage reduces kick-back noise of a subsequent latch.
A typical application of latched comparators is analog-to-digital converters (ADCs), such as successive approximation register ADCs (SAR ADCs) or sigma-delta modulation ADCs (SDM ADCs).
An important property of the comparator of a high resolution SAR ADC is the input referred noise, which is directly related to the signal-to-noise ratio (SNR) performance of the ADC. The comparator has a range where noise influences the decision no matter the sign of the difference of the input signal. This noise range needs to become smaller when the resolution of the ADC increases. Thus, for low-power, high-resolution ADCs, a low-power low-noise comparator is required.
A latched comparator according to the prior art is described in M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9 W at 1 MS/s,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, 2010.